Job Details

Mojo Vision is a Silicon Valley start-up pioneering a highly flexible, wafers-in, wafers-out micro-LED platform to unlock AI applications in multiple market segments. Built over nine years by our skilled engineers, our system-level process combines advanced 300mm silicon architecture with GaN-on-Silicon emitters, proprietary quantum dots, and micro-lens arrays to resolve conventional trade-offs in size, brightness, bandwidth density, and power. Our scalable, manufacturing-ready approach enables breakthrough products such as AI glasses and next-generation optical interconnects for AI data centers. Mojo Vision is based in Cupertino, CA.

Roles and Responsibilities:

• Design Flow Development & Automation: Developing and maintaining specialized software flows for Analog flows, front-end (RTL, simulation), and back-end (synthesis, place and route, timing) design stages.
• CAD Methodology Improvement: Evaluating and enhancing design methodologies to increase efficiency, such as implementing AI-driven design automation or customizing scripts in SKILL, Python, Tcl, or Perl to streamline repetitive tasks.
• Tool Configuration and Support: Installing, configuring, and troubleshooting Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, or Siemens-EDA to ensure they meet project-specific requirements.
• Physical Verification & Sign-off: Managing design rule checks (DRC), layout vs. schematic (LVS) verification, and parasitic extraction to ensure the chip is manufacturable (tape-out ready).
• PDK and Library Management: Maintaining Process Design Kits (PDKs) and standard cell libraries provided by foundries to ensure accurate simulation and layout.

Qualifications:

• BSEE or MSEE, and 10+ years of experience in EDA
• Tools: Expertise in major tools like Cadence, Synopsys (Virtuoso, Encounter, etc.).
• Scripting: Proficiency in SKILL, Python, Tcl, Perl for automation.
• Physical Design: Experience with DRC (Design Rule Check), LVS (Layout Versus Schematic), P&R (Place & Route), and related flows.
• Circuit Design: Understanding of digital and analog IC design principles.
• Semiconductor Process: Knowledge of fabrication processes and Device Physics.
• Programming: Familiarity with SKILL and hardware description languages (e.g., Verilog/VHDL) is often required.
• Experience in full-chip or block-level physical design.
• Developing/supporting PDKs (Process Design Kits) and PCELLs.

Valuable Additional Qualification:

• Experience with leading and mentoring layout team members

Preferred Skills:

• Strong interpersonal and problem-solving skills
• Prior experience bringing communication products to mass production

Salary Range - $188K-$230K Level: Principal Engineer