Job Details

Strongly Preferred

• 5+ years of Design Verification experience
• Deep expertise with SystemVerilog and UVM
• Experience verifying AI accelerators, GPUs, TPUs, NPUs, DSPs, or high-performance SoCs
• Strong debugging skills across RTL, simulation, and system-level failures
• Experience with constrained random verification, assertions, coverage closure, and regression infrastructure
• Experience owning DV for complex subsystems or full-chip environments

Bonus Points

• Experience with coherency protocols, memory systems, NoCs, or high-speed interfaces
• Exposure to formal verification methodologies
• Python/C++ tooling experience
• Experience improving verification productivity through automation or ML
• Startup or zero-to-one engineering experience
• Tapeout experience at advanced nodes

Compensation

We offer highly competitive cash compensation and meaningful founding-level equity packages.