Job Details

Title: Silicon Verification Engineer
Contract: 6+ Months
Location: Sunnyvale, CA, San Francisco, CA or Austin, TX (100% onsite)

Minimum Requirements:

• 7-20 years of experience, ideal range 10-15 years
• Must have a semiconductor background
• Required expertise in System Verilog and UVM
• Hands-on experience with Verilog, System Verilog, C/C++ based verification, and UVM methodology
• Experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologies
• Proven experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle

Preferred Qualifications:

• Experience developing UVM based verification environments from scratch
• Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
• Familiarity with revision control systems like Mercurial(Hg), Git or SVN
• Experience with verification of ARM/RISC-V based sub-systems or SoCs

Seniority Level:

Mid-Senior level

Employment Type:

Contract

Job Function:

Quality Assurance

Industries:

IT Services and IT Consulting